Freelance Engineer & Integrated Circuit Designer

Location:United States
2 Skills
3800 Pebble Creek Court, Apt. 614, Plano TX 75023
Tel: (310) 542-9597, Email: chintingchen@hotmail.com

Skills and Abilities:
- More than ten years of working experiences in IC circuit design and optimization.
- RFIC designs such as front end to back end receiver, LNA, I-Q Mixer, IF amplifier,
VGA, RF signal power detector; Radar signal Power detector, Log Amplifier, envelope
detector, LVDS transceiver, Line Driver, and PAM with SiGe HBT and GaAs HBT
technologies; also includes impedance match, return loss, noise, power match, stability,
power efficiency, power gain, P-1dB and IP3, frequency up to 37GHz.
- High frequency IC design such as broad bandwidth amplifier, oscillator, IQ generation,
phase detector and data/clock recovery circuits including some DLL circuitry and
CML differential digital cells with BiCMOS SiGe HBT technology.
- PLL and Synthesizer including VCO (14GHz), FPD, Charge Pump and N divider.
- CMOS IC design at transistor level of analog/Mixed Signal circuit such as low voltage
full rail to rail CMOS OpAmp, (1.8V) cascode OpAmp, folded cascode OpAmp, single
end OpAmp, BandGap voltage, constant or Ptat current source and small drop voltage
regulator and small hysteresis CMOS comparator, Delta Sigma ADC, phase detector
and loop filter.
- Resistance and capacitance on chip referencing, CMOS logic control circuit, CMOS
state Machine, counter, accumulator and initial globe reset circuit.
- RFIC device lab test, probing and measurement and bipolar transistor modeling.
- Circuit design and simulation CAD/CAE tools in Unix, NT and Linux environment.
Such as Cadence SpectreRF, ADS/Tekspice, Harmonica Balance and PSPICE on a PC.
- Script writing in Perl in Unix for digital cell library characterization.
- Software/Programming: VHDL, Verilog, VerilogA, Perl and C.

Sr. ASIC Design Engineer
Semtech (Sierra Monolithics), Redondo Beach, CA, Feb., 2006 - August, 2011
Fabless RF/High Frequency IC and module design and manufacture division.
- Design of RFIC’s such as Broad Band front end to back end receiver including LNA,
I-Q down converter, VGA and IF amplifier, frequency is up to more than 30GHz. Also
design of micro-transponder. LC Bandpass filter. With or without transmission line.
- Design of RF signal power detector, Log Amplifier, envelope detector, Radar signal
detector and analog differential comparator, some RF amplifier using spiral inductor.
- Designs of RFIC, trade for RL and impedance match on chip, gain, NF, IP3, P-1dB,
image rejection and power consumption and also for temperature compensation.
- Involved in Design and simulation of SERDES circuits (40Gbps).
- Design of PLL, Synthesizer including VCO(14GHz), PFD, Charge Pump and N divider.
- Simulations on CDR, Bang-Bang PD, DLL and design of 3.5GHz output driver.
- Simulations over temperature, power and process variations including Monte Carlo.
- Design of LVDS transceiver, low DC off set CMOS OpAmp’s (over temperature and
process variations) such as folded cascaded OpAmp and single end CMOS OpAmp.
- Design of Bandgap voltage, constant/Ptat current source and low voltage drop regulator.
- Design of on chip Resistance and Capacitance referencing, CMOS logic, CMOS state
machine and accumulator (up counter) and initial globe reset circuit.
- Design of Delta Sigma ADC.
- Design of Verilog code for PLL and VerilogA code for PLL, CDR and Analog circuits.
- IBM SiGe BiCMOS technology.
- Tool: Cadence SpectreRF, Composer, Cadence virtuoso Layout editor in Linux system.

Contract Hardware Engineer: Hewlett Packard, Vancouver, Washington.
five weeks and half in July and August, 2005.
- Testing and troubleshooting electrical engineering problems of printers.

Contract CMOS Mixed Signal Design Engineer:
Tahoe RF Semiconductor, Auburn, CA. Three weeks in May, 2005
- Designed CMOS circuits of low voltage cascode OpAmp (1.8V), small hysteresis
comparator, set-reset timer and watch dog and switched current sources for battery
charge and power management.
- Designed state machine and control ?logic for battery charge and power
- Tools: Cadence SpectreS and composer.

Hardware Engineer (IC Design): Tektronix, Beaverton, OR. 10/2000 - 12/2002
High Frequency IC Design group (BiCMOS SiGe HBT technology).
- Design of High Frequency ASIC such as broad bandwidth Amplifiers, ring oscillator, I
Q generator, data and clock recovery circuitry (up to 10ghz) and some DLL circuitry
including voltage controlled delay cell, phase detector and loop filter at transistor level.
- Design and characterization of Differential digital cells (up to 10ghz) at transistor level.
- Wrote scripts and test benches in Verilog and Perl for auto-batch simulation on CML
differential logic cells.
- Design of layouts of High Frequency amplifier, ring oscillator and digital cell IC’s.
- CAD tool and Software: ADS and Tekspice, Debussy, ICEDIT, Verilog and Perl.

Component Design Engineer: Intel Corporation, Aloha, OR. 4/99 - 10/2000
Server and Workstation Chip set Design group (CMOS technology).
- Design and implement of RTL of Data Path, on chip register file RAM, RAM array,
ECC and BIST for CDM with VHDL. Script writing in C for design.
- Built up test benches and verified Data Path, RAM Array, ECC and CDM at RTL level.
- Extracting critical path timing information and improving timing with Prime Time and
some of synthesis process. 0.18u CMOS technology and 800 MHz clock rate.
- Validated customized circuit designs or synthesized gate circuits against RTL design.
- Tools: Renoir, ModelSim, Prime Time, Design Verifyer, Shark and some of Design

Design Engineer: EIC, Fremont, CA. 1997 - 3/99
A RFIC design and manufacturing company (GaAs HBT technology).
- Design and simulation of Mixer, LNA, VGA, Line Drivers including Darlington
amplifier and PAM at transistor level including impedance match, noise match, power
match, stability, power efficiency, power gain, conversion gain, I/O isolation, adjacent
channel and IP3.
- Did modeling of GaAs HBT transistor and built up transistor model for RFIC design.
- Did transistor probing, RFIC device lab testing and measurements with network
- Design of RFIC layouts and DRC and LVS checks.
- CAD Tools: Harmonica Balance and PSPICE on a PC.

Design Engineer: AKM Design Tek, San Diego, CA. 1/96 - 1/97
A CMOS IC design company (CMOS technology).
- Designed and optimized CMOS IC subsystems at transistor level such as ROM, SRAM
including array, RAM cell, equalizer, word line decoder, address decoder and control
logic and sense amplifier.
- Designed CMOS analog OpAmp and chip interface I/O buffers at transistor level.
- Designed, characterized and optimized CMOS cells at transistor level such as I/O
Buffers, dynamic/static flip-flop, Schmidt Trigger, Latch, MUX, State Machine
including up counter, down counter and complex logic.
- Clock circuitry design and clock skew alignment such as clock drive alignment.
- Did replacing VHDL synthesized and generated gate level subsystems with tilable cells.
- Tools: HSPICE, NOVA and Dracula on a SUN/UNIX station.

Contract Engineer: E. F. Johnson Company, Waseca, MN. 1/95 - 10/95
A mobile dispatch radio designer and manufacturer.
- Was involved in design and development of a Dual Mode of Cellular - Mobile radio
System (900 MHz, 15W), including logic/audio circuits, interface circuitry.
- Tested whole system including Cellular and Mobile radios, emulator and interface
circuitry with tools of communication network and oscilloscope, etc.

Technical Staff of Digital Group: Tatung Telecom, Mountain View, CA. 1/94 - 9/94
A pay phone manufacturer and Digital Cordless Telephone designer and developer.
- Was involved in design of power management, telephone trunk interface, malfunction
indicator and logic/audio circuitry with 80C51uP, CT2, FPGA, memory and 32KHz bit
rate chips at board level.
- Tools: OrCad and Viewlogic on a PC, digital network analyzer and spectrum analyzer.

OGI (Oregon Graduate Institute), 2001,
- Completed course work: Analog CMOS IC design and its project. (Grade: A-).
- Completed the project of a 3V full rail-to-rail CMOS OpAmp.

Master degree in Electrical Engineering; 3.8 G.P.A.
- The City College of the City University of New York.
- Major: Integrated Circuit design, RF system and Microwave

Bachelor degree in Electrical Engineering
- The North China Institute of Electric Power. Bao Ding City, China.