Robert Shawn Hector

Freelance Electrical Engineer & Analog Engineer

1590
Location:Sebastopol, California, United States
Profile:https://www.freelanced.com/robertshawnhector
0
Kudos
4.5
2 Skills
$85
Rate/Hr
Robert Shawn Hector
13215 Fiori Lane
Sebastopol, CA 95472
rshawnh@yahoo.com
408-891-0003
1
Results-oriented Engineer with board expertise in Mixed-Signal, Digital, and Analog Circuit Design and a
strong natural inclination toward leadership, my involvement starts at specification, and generally continues
past evaluation. Strong Systems and Top-Level design skills have lead me to designing Integrated Circuits and
FPGA’s in a variety of application areas including Video, Audio, Imaging, and Communications. In all of these
designs strong team building and leadership skills were critical in meeting schedule and product specifications.
Experience:
InVisage Inc. – Menlo Park, CA Winter – 2012/2013
Mixed Signal Verification Engineer - Consultant
Responsible for System and Top-Level Modeling and Verification of analog and mixed-signal Imaging
systems.
Intersil Corporation/Xicor – Milpitas, CA Summer 2005-Fall 2012 (Intersil acquired Xicor in Summer 2005)
Senior Staff Mixed Signal Design Engineer
Responsible for System and Top-Level Design of analog and mixed-signal systems. I have been a technical
and collaborative lead through all phases of the CMOS IC design process. The following include projects at
Intersil:
• SAR ADC Applications Engineering – 1MHz SAR Evaluation Environment – technical lead
o Python GUI development, USB Driver, ADC Evaluation Software
o Xilinx FPGA Programming, 8051 Development, Embedied Design
o Multiple PCB Designs
o Research and Outlined Company-wide Evaluation Platform
o Lead Jr. Engineers in Application duties
• HDMI/DVI Repeater - 2.2Gbits/s LVDS in 0.18um CMOS – technical lead
o Top-Level architecture, integration, and Circuit Design
o Top-Level simulation and verification(VMM)
o Advised and lead analog and digital engineers to meet block level specification
o Research and Outlined HDMI specification to designers
o FPGA Design Verification
• Video/Imaging Analog Front End - 170 MHz 10 bits in 0.18um CMOS – technical lead
o Flash ADC system design – performance optimizations and design
o Top-Level Design and Verification
o Digital Design – Dither, Encoder
• ADC - Sigma Delta – 12 bit resolution 12 oversampling 25 MHz bandwidth
o System Modeling using Matlab,Verilog A, and Spice
o Top Level assembly
o Circuit Design of Second Order Modulator Loop
• Pipeline – 14 bit 100 Mhz in 0.18u
o Verification and simulation of top-level
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Xicor/AIP - Milpitas, CA Summer 2002 – Summer 2005 (Xicor acquired AIP in Summer 2003)
Staff Mixed Signal Design Engineer – technical lead
Responsible for System and Top-Level Design of analog/mixed-signal system including:
• Video/Imaging Analog Front End - 300 MHz 8 bits in 0.18um CMOS
o Flash ADC system design – Timing and performance optimizations
o Top-Level Design and Verification
o Circuit Design – comparators, controls, timing circuits, ADC Encoders
• Video/Imaging Analog Front End - 170 MHz 10 bits in 0.18um CMOS
o Flash ADC system design – performance optimizations
o Top-Level Design and Verification
• Advised and lead analog and digital engineers to meet block level specifications
Analog Integration Partners - Milpitas CA Spring 99 - Summer 2002
Staff Mixed Signal Design Engineer
I was responsible for Digital, Analog, and System Circuit Design of Mixed Signal Intellectual Property
including:
• Video/Imaging Analog Front End -225 MHz 8 bits in 0.25um CMOS
o Flash ADC system design
o DSP – Color Space Converter, Automatic Black Level Control, Dither
o Top-Level Design and Modeling- Top Level assembly and integration
o Circuit Design – ADC timing circuits, ADC Encoders, Analog Circuitry
o Digital Design – I2C,Controls, Digital PLL, Sync Processor
o Researched and design I2C from specification
• Flash, Sigma Delta, Pipeline ADC’s – 1MHz to 50MHz with 8 to12 bits of resolution
o System Modeling using Matlab,Verilog A, and Spice
o Top-Level Circuit Design
o Top-Level Verification
• 1 GB Ethernet AFE – Full duplex, 250 MHz 5 bit ADC in 0.18u CMOS
o Analog Filter Design – LC Ladder using Operation Simulation 75 MHz -3dB point
with a 6dB peaking at 50Mhz
o System Verification – Verified design using Spice
o System Modeling using Matlab to find design trade-offs
o Amplifier Design
• Intellectual Property Transfers - Worked directly and closely with customers to understand specification
and requirements. Delivered GDS, schematics, verilog, and modeling information to customers
• Design behavioral models for ADC’s, DAC’s, PLL’s, VCO’s and other mixed-signal systems
• Implemented Digital Design flow for small circuit design group
• Lead both consultants and employees to the completion of many projects
Aureal Semiconductor – Fremont, CA Fall 98
Senior Digital Design Engineer
I was responsible for RTL Design and Verification of Audio Processors.
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INVOX - Cupertino, CA Spring 98
Applications Engineer
Responsible for engineering support to sales and marketing including:
• Designed customer application boards
• Traveled both domestic and internationally
• Maintain technical and business relationship with customers
• Supported INVOX design wins from design through board bring-up
Rendition - Santa Clara, CA Fall 97
Digital Design Engineer
Responsible for Circuit design of CAM’S and FIFO’s for Graphics Processors
Exar – Fremont, CA Spring 94- Fall 97
Senior Design Engineer
Responsible for Design and Verification of Mixed-Signal Imaging Circuits including:
• Scanner Analog Front Ends
• Camera SOC – Digital Photo Camera SOC
• ADC – Flash, Pipeline, and Successive Approximation
• FPGA Design and Prototype
MicroPower Systems - Santa Clara, CA Summer 93-Spring 94
Engineering Intern/ Design Engineer
Designed and characterized mixed-signal circuits.
Design and Productivity Tools:
Cadence Design Tools, Analog Artist, Verilog, Verilog A, Verilog AMS, SystemVerilog, Spice,
Nanosim, Spectre, Perl, Python, Matlab, C, Microsoft Office tools, Design Compiler, Behavioral Compiler,
Primetime, Synopsys LIB file generation, Protel, Xilinx’s and Actel Tools
Education:
George Washington High School – Graduated General Education 1988
City College of San Francisco – Transferred 1990
University of the Pacific - Graduated Bachelors of Science in Engineering Physics 1994
University of Essex- Research at the Center of Audio Engineering and Design Winter 1995